RADSAGA back to ChipIr with brand new experiments

On March 12-16, 2020, one year after the first test campaign, the RADSAGA ESRs went back to the ISIS Neutron and Muon Source at the Rutherford Appleton Laboratory (RAL) in Didcot, UK. The RADSAGA ESRs on site were Daniel Söderström (ESR 02), Kimmo Niskanen (ESR 07) and Mohamed Mounir Mahmoud (ESR 08).

At the ISIS Neutron and Muon Source, there is a dedicated neutron beam line for electronics testing called ChipIR (more info here), which provides neutrons with an energy spectrum similar to the neutron spectrum found in the atmosphere.

At the ChipIR beam line, Daniel, together with Lucas Matana Luza from Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier (LIRMM), tested the response of different types of memories to the atmospheric neutrons. The tested memories were Random Access Memories (RAM): HyperRAM which uses the HyperBus interface, and SDRAM which is a Synchronous Dynamic RAM.For the SDRAM, the tests were done primarily to study the degradation of the memory cells, and to study how the memory’s ability to store the correct data in the memory cells would deteriorate as more and more neutrons would hit the memory and damage it. The testing of the HyperRAM consisted of two parts. One part was static and dynamic tests, where data patterns were written to the memory before an irradiation run started, and read back after the beam was shut off again (static), or written and read to the memory over and over during irradiation (dynamic). The other part was that an image recognition algorithm in a neural network was applied during the neutron irradiation, to simulate the memory usage in a real case scenario. Here the images, and parts of the neural network, were stored on the HyperRAM as the image recognition was running under neutron irradiation. Failures in the recognition algorithm will then be correlated with the failure modes found in the static and dynamic tests.

Kimmo performed experiments on latest generation SiC power MOSFETs. The aim of the experiment was to study the effect of gate bias voltage on the single event burnout (SEB) sensitivity. A total of 150 DUTs were tested with different drain and gate bias voltages applied during irradiation. The experiment was conducted in a destructive manner (i.e. the devices were broken and unusable after the test), and the fluence to failure values were determined for each device in order to determine the failure rate under the atmospheric neutron spectrum.

Mohamed conducted an accelerated aging radiation test on an internally designed test structure chip. The experiment was performed to investigate the impact of aging degradation mechanisms on the radiation susceptibility of digital integrated circuits of advanced technology nodes. The test structure chip is made of four programmable arrays of transistors, and six shift register chains in a 28 nm UTBB FD-SOI technology node. Before the radiation test, an accelerated aging process was performed on one test chip, by stressing it for 30 hours with 150 % of the nominal voltage, in a 120 °C controlled climate chamber. Two test structures were irradiated for 36 hours in parallel: a fresh test structure, and the pre-aged test structure. The single event upsets induced by the neutron irradiation in both test structures were monitored using specially designed PCBs that were controlled by a Xilinx FPGA/ARM SoC.

ESR02 Daniel Söderström, ESR07 Kimmo Niskanen, ESR08 Mohamed Mounir Mahmoud

Here are some pictures from the test campaign:

Daniel & Mohamed